View SI5013_1590119.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. 1.4 5/05 copyright ? 2005 by silicon laboratories SI5013 SI5013 oc-12/3, stm-4/1 sonet/sdh cdr ic with l imiting a mplifier features h igh-speed clock and data recovery devic e with integrated limiting amplifier: applications description the SI5013 is a fully-integrated, high-per formance limiting amplifier (la) and clock and data recovery (cdr) ic for high-speed serial communication systems. it derives timing information and data from a serial input at oc-12/3 and stm-4/1 rates. use of an external reference clock is optional. silicon laboratories? dspll ? technology eliminates sensitive nois e entry points, thus making the pll less susceptible to board-level interactio n and helping to ensure optimal jitter performance. the SI5013 represents a new standard in low jitter, low power, small size, and integration for high-speed la/cdrs. it operates from a 3.3 v supply over the industrial temperature range (?40 to 85 c). functional block diagram supports oc-12/3, stm-4/1 dspll? technology jitter generation 2.3 mui rms (typ) small footprint: 5 x 5 mm reference and reference-less operation supported loss-of-signal level alarm data slicing level control 10 mv pp differential sensitivity 3.3 v supply sonet/sdh/atm routers add/drop multiplexers digital cross connects board level serial links sonet/sdh test equipment optical transceiver modules sonet/sdh regenerators limiting amp dspll lock detection retimer reset/ calibration bias gen. buf buf clkout+ clkout? din+ din? refclk+ refclk? (optional) los lol rext reset/cal slice_lvl dsqlch clk_dsbl ltr ratesel signal detect los_lvl ber_lvl ber monitor dout+ dout? 2 2 2 2 ber_alm ordering information: see page 21. pin assignments SI5013 gnd pad 1 2 3 4 5 gnd los_lvl refclk+ ratesel slice_lvl 6 7 lol refclk? 21 20 19 18 17 rext reset/cal dout+ vdd vdd 16 15 tdi dout? 8 9 10 11 12 los dsqlch din+ ltr vdd 13 14 vdd din? 28 27 26 25 24 ber_alm ber_lvl clkdsbl nc vdd 23 22 clkout? clkout+
SI5013 2 rev. 1.4
SI5013 rev. 1.4 3 t able of c ontents section pag e 1. detailed block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3. typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 4.1. limiting amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2. dspll? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3. multi-rate operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 4.4. operation without an ex ternal reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.5. operation with an external refer ence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 4.6. lock detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 4.7. lock-to-reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.8. loss-of-signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.9. bit error rate (ber) detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.10. data slicing level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.11. pll performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.12. reset/dspll calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.13. clock disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 4.14. data squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 4.15. device grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.16. bias generation circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.17. voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.18. differential input ci rcuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.19. differential output circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5. pin descriptions: SI5013 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7. package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
SI5013 4 rev. 1.4 1. detailed block diagram slicing control signal detect phase detector a/d limiting amp n dsp vco clk dividers lock detection retime ber monitor din+ din? refclk (optional) ltr slice_lvl los_lvl ratesel calibration reset/cal clkout+ dout+ clkout? dout? clkdsbl ber_alm ber_lvl los lol dsqlch bias generation rext
SI5013 rev. 1.4 5 2. electrical specifications figure 1. differential voltage measurement (din, refclk, dout, clkout) table 1. recommended operating conditions parameter symbol test condition min 1 typ max 1 unit ambient temperature t a ?40 25 85 c SI5013 supply voltage 2 v dd 3.135 3.3 3.465 v notes: 1. all minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. typical values apply at nominal supply voltages and an operating temperature of 25 c unless otherwise stated. 2. the SI5013 specifications are guarant eed when using the recommended application circuit (including component tolerance) of "3.typical application schematic" on page 11. 0.5 v id signal+ signal? v id b. operation with differential inputs and outputs v is a. operation with single-ended inputs signal+ signal? v t v t (signal+) ? (signal?) dout t cr-d t cf-d clkout
SI5013 6 rev. 1.4 figure 2. clock to data timing figure 3. dout and clkout rise/fall times figure 4. pll acquisition time figure 5. los response dout, clkout t f t r 80% 20% t aq reset/cal lol datain t aq lol datain los threshold level t los los
SI5013 rev. 1.4 7 table 2. dc characteristics (v dd = 3.3 v 5%, t a = ?40 to 85 c) parameter symbol test condition min typ max unit supply current 1 oc-12 oc-3 i dd ? ? 180 190 190 197 ma power dissipation oc-12 oc-3 p d ? ? 594 627 657 682 mw common mode input voltage (din) 2 v icm see figure 11 ? 1.50 ? v common mode input voltage (refclk) 2 v icm see figure 10 1.90 2.10 2.30 v din single-ended input voltage swing 2 v is see figure 1a 10 ? 500 mv din differential input voltage swing 2 v id see figure 1b 10 ? 1000 mv refclk single-ended input voltage swing 2 v is see figure 1a 200 ? 750 mv refclk differential input voltage swing 2 v id see figure 1b 200 ? 1500 mv input impedance (din) r in line-to-line 84 100 116 ? differential output voltage swing (dout) v od 100 ? load line-to-line 700 800 1150 mv pp differential output voltage swing (clkout) v od 100 ? load line-to-line 700 800 1150 mv pp output common mode voltage (dout, clkout) v ocm 100 ? load line-to-line 1.6 1.95 2.35 v output impedance (dout,clkout) r out single-ended 84 100 116 ? input voltage low (lvttl inputs) v il ?? .8 v input voltage high (lvttl inputs) v ih 2.0 ? ? v input low current (lvttl inputs) i il ??10a input high current (lvttl inputs) i ih ??10a input impedance (lvttl inputs) r in 10 ? ? k ? los_lvl, ber_lvl, slice_lvl input impedance r in 75 100 125 k ? output voltage low (lvttl outputs) v ol i o =2ma ? ? 0.4 v output voltage high (lvttl outputs) v oh i o =2ma 2.0 ? ? v notes: 1. no load on lvttl outputs. 2. these inputs may be driven differentially or single-endedl y. when driven single-endedly, the unused input must be ac coupled to ground.
SI5013 8 rev. 1.4 table 3. ac characteristics (clock and data) (v dd =3.3v 5%, t a = ?40 to 85 c) parameter symbol test condition min typ max unit output clock rate f clk rate sel = 1 rate sel = 0 616 154 ? ? 675 158 mhz output rise time?oc-12 t r figure 3 ? 125 155 ps output fall time?oc-12 t f figure 3 ? 125 155 ps output clock duty cycle? oc-12/3 47 50 53 % of ui clock to data delay oc-12 oc-3 t cr-d figure 2 800 4000 840 4100 900 4200 ps clock to data delay oc-12 oc-3 t cf-d figure 2 10 800 35 850 60 1000 ps input return loss 100 khz?622 mhz ?15 ? ? db slicing level offset 1 (relative to the internally set input common mode voltage) v slice slice_lvl = 750 mv to 2.25 v ?15 ? 15 mv slicing level accuracy slice_lvl = 750 mv to 2.25 v ? 5 ? mv loss-of-signal range 2 (peak-to-peak differential) v los los_lvl = 1.50 to 2.50 v 0 ? 40 mv loss-of-signal response time t los figure 5 on page 6 8 20 25 s notes: 1. adjustment voltage (relative to the internally set i nput common mode voltage) is calculated as follows: v slice = (slice_lvl ? 1.50)/50. 2. adjustment voltage is calculated as follows: v los = (los_lvl ? 1.50)/25.
SI5013 rev. 1.4 9 table 4. ac characteristics (pll characteristics) (v dd = 3.3 v 5%, t a = ?40 to 85 c) parameter symbol test condition min typ max unit jitter tolerance (oc-12 mode) * j tol(pp) f = 30 hz 60 ? ? ui pp f=300hz 6 ? ? ui pp f=25khz 4 ? ? ui pp f = 250 khz 0.4 ? ? ui pp jitter tolerance (oc-3 mode) * j tol(pp) f = 30 hz 60 ? ? ui pp f=300hz 6 ? ? ui pp f=6.5khz 4 ? ? ui pp f=65khz 0.4 ? ? ui pp rms jitter generation * j gen(rms) with no jitter on serial data ? 2.3 4.0 mui peak-to-peak jitter generation * j gen(pp) with no jitter on serial data ? 20 45 mui jitter transfer bandwidth * j bw oc-12 mode ? ? 500 khz oc-3 mode ? ? 130 khz jitter transfer peaking * j p ?0.030.1db acquisition time?oc-12 (reference clock applied) t aq after falling edge of pwrdn/cal ?1.5 2 ms from the return of valid data ?60 ?s acquisition time?oc-12 (reference-less operation) t aq after falling edge of pwrdn/cal ?4.012ms from the return of valid data ?13 ?ms reference clock range see "4.4.operation with- out an external refer- ence" on page 12. 155.5 77.76 19.44 mhz input reference clock frequency tolerance c tol ?500 ? 500 ppm frequency difference at which receive pll goes out of lock (refclk compared to the divided down vco clock) ?650 ?ppm *note: as defined in bellcore specifications: gr-253- core, issue 3, septem ber 2000. using prbs 2 23 ? 1 data pattern.
SI5013 10 rev. 1.4 table 5. absolute maximum ratings parameter symbol value unit dc supply voltage v dd ?0.5 to 3.5 v lvttl input voltage v dig ?0.3 to 3.6 v differential input voltages v dif ?0.3 to (v dd + 0.3) v maximum current any output pin 50 ma operating junction temperature t jct ?55 to 150 c storage temperature range t stg ?55 to 150 c esd hbm tolerance (100 pf, 1.5 k ? )1kv note: permanent device damage may occur if the above absolu te maximum ratings are exceeded. functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 6. thermal characteristics parameter symbol test condition value unit thermal resistance junction to ambient ? ja still air 38 c/w
SI5013 rev. 1.4 11 3. typical application schematic SI5013 lvttl control inputs loss-of-lock indicator lol high-speed serial input system reference clock (optional) din+ din? refclk+ refclk? rext vdd gnd dout+ dout? clkout+ clkout? recovered data recovered clock 100 pf x 4 0.1 f vdd ber alarm indicator ber_alm loss-of-signal indicator los 10 k ? slice_lvl data slice level set ber_lvl bit error rate level set los_lvl loss-of-signal level set ltr clkdsbl ratesel reset/cal dsqlch
SI5013 12 rev. 1.4 4. functional description the SI5013 integrates a high-speed limiting amplifier with a multi-rate cdr unit. no external reference clock is required for clock and data recovery. the limiting amplifier magnifies very lo w-level input data signals so that accurate clock a nd data recovery can be performed. the cdr uses silicon laboratories? dspll technology to reco ver a clock synchronous to the input data stream. the re covered clock retimes the incoming data, and both are output synchronously via current-mode logic (cml) dr ivers. silicon laboratories? dspll technology ensures superior jitter performance while eliminating the need for external loop filter components found in traditional phase-locked loop (pll) implementations. the limiting amplifier incl udes a control input for adjusting the data slicing le vel and provides a loss-of- signal level alarm output. the cdr includes a bit error rate performance monitor which signals a high bit error rate condition (associated with excessive incoming jitter) relative to an externally adjustable bit error rate threshold. the optional reference clock minimizes the cdr acquisition time and provides a stable reference for maintaining the output clock wh en locking to a reference is desired. 4.1. limiting amplifier the limiting amplifier accepts the low-level signal output from a transimpedance amplifier (tia). the low-level signal is amplified to a usable level for the cdr unit. the minimum input swing requirement is specified in table 2 on page 7. larger input amplitudes (up to the maximum input swing specified in table 2) are accommodated without degradation of performance. the limiting amplifier ensures optimal data slicing by using a digital dc offset cancellation technique to remove any dc bias introduced by the amplification stage. 4.2. dspll ? the SI5013 pll structure (shown in the "1.detailed block diagram" on page 4) utilizes silicon laboratories' dspll technology to maintain superior jitter performance while eliminating the need for external loop filter components found in traditional pll implementations. this is achieved using a digital signal processing (dsp) algorithm to replace the loop filter commonly found in analog pll designs. this algorithm processes the phase detector error term and generates a digital control value to adjust the frequency of the voltage-controlled oscillato r (vco). this technology enables cdr with far less jitte r than is generated using traditional methods, and it eliminates performance degradation caused by external component aging. in addition, because external loop filter components are not required, sensitive noise entry points are eliminated, thus making the dspll less susceptible to board-level noise sources and making sonet/sdh jitter compliance easier to atta in in the application. 4.3. multi-rate operation the SI5013 supports clock and data recovery for oc- 12/3 and stm-4/1 data streams. multi-rate operation is achieved by configuring the device to divide down the output of the vco to the desired data rate. the divide factor is configured by the ratesel pin. the ratesel configuration and associated data rates are given in table 7. 4.4. operation without an external refer- ence the SI5013 can perform clock and data recovery without an external refe rence clock. tying the refclk+ input to vdd and the refclk? input to gnd configures the device to operate without an external reference clock. clock recovery is achieved by monitoring the timing quality of the incoming data relative to the vco frequency. lock is maintained by continuously monitoring the incoming data timing quality and adjusting the vco accordingly. details of the lock detection and the lock-to-reference functions while in this mode are described in their respective sections below. note: without an external reference the acquisition of data is dependent solely on the data itself and typically requires more time to acquire lock than when a refer- ence is applied. 4.5. operation with an external reference the SI5013 can also perform clock and data recovery with an external reference. the device?s optional external reference clock centers the dspll, minimizes the acquisition time, and main tains a stable output clock (clkout) when lock-to-reference (ltr ) is asserted. when the reference clock is present, the SI5013 uses the reference clock to center the vco output frequency so that clock and data is recovered from the input data stream. the device self configures for operation with one of three reference clock frequencies. this table 7. multi-rate configuration ratesel sonet/sdh 1622.08mbps 0155.52mbps
SI5013 rev. 1.4 13 eliminates the need to externally configure the device to operate with a particular reference clock. the refclk frequency should be 19.44, 77.76, or 155.52 mhz with a frequency accuracy of 100 ppm. 4.6. lock detect the SI5013 provides lock-detect circuitry that indicates whether the pll has achieved frequency lock with the incoming data. the operation of the lock-detector depends on the reference clock option used. when an external reference clock is provided, the circuit compares the frequency of a divided-down version of the recovered clock with the frequency of the applied reference clock (refclk). if the recovered clock frequency deviates from that of the reference clock by the amount specified in table 4 on page 9, the pll is declared out of lock, and the loss-of-lock (lol ) pin is asserted. in this state, th e pll will periodically try to reacquire lock with the incoming data stream. during reacquisition, the recovered clock frequency (clkout) drifts over a 600 ppm range relative to the applied reference clock and the lol output alarm may toggle until the pll has reacquired frequency lock. due to the low noise and stability of the dspll, th ere is the possibility that the pll will no t drift enough to render an out-of-lock condition, even if the data is removed from inputs. in applications requiring a more stable output clock during out-of-lock conditions, the lock-to-reference (ltr ) input can be used to force the pll to lock to the externally supplied reference. in the absence of an external reference, the lock detect circuitry uses a data quality measure to determine when frequency lock has been lost with the incoming data stream. during reacquisition, clkout may vary by approximately 10% from the nominal data rate. 4.7. lock-to-reference the ltr input can be used to force a stable output clock when an alarm condition, like los, exists. in typical applications, the los output is tied to the ltr input to force a stable output clock when the input data signal is lost. when ltr is asserted, the dspll is prevented from acquiring the data signal present on din. the operation of the ltr control input depends on which reference clocking mode is used. when an external reference clock is present, assertion of ltr forces the dspll to lock clkout to the provided reference. if no external reference clock is used, ltr forces the dspll to hold the digital frequency control input to the vco at the last value. this produces a stable output clock as long as supply and temperature are constant. 4.8. loss-of-signal the SI5013 indicates a loss-of-signal condition on the los output pin when the input peak-to-peak signal level on din falls below an externally controlled threshold. the los threshold range is specified in table 3 on page 8 and is set by applying a voltage on the los_lvl pin. the graph in figure 6 illustrates the los_lvl mapping to the los threshold. the los output is asserted when the input signal drops below the programmed peak-to-peak value. if desired, the los function may be disabled by grounding los_lvl or by adjusting los_lvl to be less than 1 v. figure 6. los_lvl mapping figure 7. los signal hysteresis in many applications it is desirable to produce a fixed amount of signal hysteresis for an alarm indicator such as los , since a marginal data input signal could cause intermittent toggling, leading to false alarm status. when it is anticipated that very low-level din signals will be encountered, the introduction of an adequate amount of los hysteresis is recommended to minimize any undesirable los signal to ggling. figure 7 illustrates a simple circuit that may be used to set a fixed level of los signal hysteresis for the SI5013 cdr. the value of 40 mv/v 0 mv 0 v los_lvl (v) los threshold (mv pp ) 30 mv 2.25 v 1.50 v 1.00 v 15 mv los disabled los undefined 1.875 v 40 mv 2.5 v 9 3 los los_lvl r1 r2 10k SI5013 cdr los alarm set los level
SI5013 14 rev. 1.4 r1 may be chosen to provide a range of hysteresis from 3 to 8 db where a nominal value of 800 ? adjusts the hysteresis level to approximately 6 db. use a value of 500 ? or 1000 ? for r1 to provide 3 db or 8 db of hysteresis, respectively. hysteresis is defined as the ratio of the los deassert level (losd) and the los assert level (losa). the hysteresis in decibels is calculated as 20log(losd/ losa). 4.9. bit error ra te (ber) detection the SI5013 uses a proprie tary silicon laboratories? algorithm to generate a bit error rate (ber) alarm on the ber_alm pin if the observed ber is greater than a user programmable threshold. bit error detection relies on the input data edge timing; edges occurring outside of the expected event window are counted as bit errors. the ber threshold is programmed by applying a voltage to the ber_lvl pin between 500 mv and 2.25 v corresponding to a ber of approximately 10 ?10 and 10 ?6 , respectively. the voltage present on ber_lvl maps to the ber as follows: log10(ber) = (4 x ber_lvl) ?13. (ber_lvl is in volts; ber is in bits per second.) 4.10. data slicing level the SI5013 provides the ability to externally adjust the slicing level for applications that require bit error rate (ber) optimization. adjust ments in slicing level of 15 mv (relative to the in ternally set input common mode voltage) are supported. the slicing level is set by applying a voltage between 0.75 and 2.25 v to the slice_lvl input. the voltage present on slice_lvl maps to the slicing level as follows: where v slice is the slicing level, and v slice_lvl is the voltage applied to the slice_lvl pin. when slice_lvl is driven below 500 mv, the slicing level adjustment is disabled, and the slicing level is set to the cross-point of the differential input signal. 4.11. pll performance the pll implementation used in the SI5013 is fully compliant with the jitter specifications proposed for sonet/sdh equipment by bellcore gr-253-core, issue 3, september 2000 and itu-t g.958. 4.11.1. jitter tolerance the SI5013?s tolerance to inpu t jitter exceeds that of the bellcore/itu mask shown in figure 8. this mask defines the level of peak-t o-peak sinusoid jitter that must be tolerated when applied to the differential data input of the device. figure 8. jitter tolerance specification 4.11.2. jitter transfer the SI5013 exceeds all relevant bellcore/itu specifications related to sonet/sdh jitter transfer. jitter transfer is defined as th e ratio of output signal jitter to input signal jitter as a function of jitter frequency. these measurements are made with an input test signal that is degraded with sinu soidal jitter whose magnitude is defined by the mask in figure 9. figure 9. jitter transfer specification v slice v slice_lvl 1.5 v ? () 50 ------------------------------------------------------- = 15 1.5 0.15 f0 f1 f2 f3 ft sinusoidal input jitter (ui pp ) frequency slope = 20 db/decade f0 (hz) f1 (hz) f2 (khz) sonet data rate oc-12 oc-3 f3 (khz) ft (khz) 10 10 30 30 300 300 25 250 6.5 65 0.1 db jitter transfer fc frequency 20 db/decade slope fc (khz) sonet data rate oc-12 oc-3 500 130 acceptable range
SI5013 rev. 1.4 15 4.11.3. jitter generation the SI5013 exceeds all relevant specifications for jitter generation proposed for sonet/sdh equipment. the jitter generation specification defines the amount of jitter that may be present on the recovered clock and data outputs when a jitter free input signal is provided. the SI5013 typically generates less than 3.0 mui rms of jitter when presented with ji tter-free input data. 4.12. reset/ds pll calibration the SI5013 achieves opti mal jitter performance by automatically calibrating the loop gain parameters within the dspll on powerup. calibration may also be initiated by a hi gh-to-low transiti on on the reset/cal pin. the reset/cal pin must be held high for at least 1 s. when reset/cal is rele ased (set to low) the digital logic resets to a known initial condition, recalibrates the dspll, and begins to lock to the incoming data stream. for a valid reset to occur when using reference mode, a proper, external reference clock frequency must be applied. 4.13. clock disable the SI5013 provides a clock disable pin (clk_dsbl) that is used to disable the recovered clock output (clkout). when the clk_dsbl pin is asserted, the positive and negative terminals of clkout are tied to vdd through 100 ? on-chip resistors. 4.14. data squelch the SI5013 provides a data squelching pin (dsqlch) that is used to set the recovered data output (dout) to binary zero. when the dsqlch pin is asserted, the dout+ signal is held low and the dout? signal is held high. this pin can be is used to squelch corrupt data during los and lol situations. care must be taken when ac coupling these outputs; a long string of zeros or ones will not be held th rough ac coupling capacitors. 4.15. device grounding the SI5013 uses the gnd pad on the bottom of the 28- pin micro leaded package (mlp) for device ground. this pad should be connected directly to the analog supply ground. see figure 15 on page 18 and figure 16 on page 22 for the ground (gnd) pad location. 4.16. bias generation circuitry the SI5013 makes use of an external resistor to set internal bias currents. the external resistor allows precise generation of bias currents which significantly reduces power consumption versus traditional implementations that use an internal resistor. the bias generation circuitry requires a 10 k ? (1%) resistor connected between rext and gnd. 4.17. voltage regulator the SI5013 operates from a 3.3 v external supply voltage. internally the device operates from a 2.5 v supply. the SI5013 regulates 2.5 v internally down from the external 3.3 v supply. in addition to supporting 3.3 v systems, the on-chip linear regulator offers be tter power supply noise rejection versus a direct 2.5 v supply. 4.18. differential input circuitry the SI5013 provides differential inputs for both the high- speed data (din) and the reference clock (refclk) inputs. an example termination for these inputs is shown in figures 10 and 11, respectively. in applications where direct dc coupling is possible, the 0.1 f capacitors may be omitted. (los operation is only guaranteed when ac coupled.) the data input limiting amplifier requires an input signal with a differential peak-to-peak voltage as specified in table 2 on page 7 to ensure a ber of at least 10 ?12 . the refclk input differential peak-to-peak voltage requirement is also specified in table 2.
SI5013 16 rev. 1.4 figure 10. input termination for refclk (ac coupled) figure 11. input termination for din (ac coupled) figure 12. single-ended input termination for refclk (ac coupled) clock source SI5013 0.1 f 0.1 f zo = 50 ? zo = 50 ? rfclk+ rfclk? 2.5 k ? 2.5 k ? 10 k ? 10 k ? 100 ? gnd 2.5 v (5%) tia SI5013 0.1 f 0.1 f zo = 50 ? zo = 50 ? din+ din? 5 k ? 50 ? gnd 7.5 k ? 50 ? 2.5 v (5%) 0.1 f clock source SI5013 0.1 fzo = 50 ? rfclk + rfclk ? 2.5 k ? 2.5 k ? 10 k ? 10 k ? 50 ? gnd 2.5 v (5%)
SI5013 rev. 1.4 17 figure 13. single-ended input termination for din (ac coupled) 4.19. differential output circuitry the SI5013 utilizes a curren t-mode logic (cml) ar chitecture to output both th e recovered clock (clkout) and data (dout). an example of output termination with ac coupling is shown in figure 14. in applications in which direct dc coupling is possible, the 0.1 f capacitors may be omitted. the diff erential peak-to-peak voltage swing of the cml architecture is specified in table 2 on page 7. figure 14. output termination for dout and clkout (ac coupled) SI5013 0.1 f zo = 50 ? din+ din? 5 k ? 50 ? gnd 7.5 k ? 50 ? 2.5 v (5%) ? 100 0.1 f signal source dout?, clkout? 50 ? 50 ? 0.1 f 0.1 f zo = 50 ? zo = 50 ? SI5013 vdd vdd 100 ? 100 ? 2.5 v (5%) dout+, clkout+ 2.5 v (5%)
SI5013 18 rev. 1.4 5. pin descriptions: SI5013 figure 15. SI5013 pin configuration table 8. SI5013 pin descriptions pin # pin name i/o signal level description 1 ratesel i lvttl data rate select. this pin configures the onboard pll for clock and data recovery at one of two user selectable data rates. see table 7 for configuration settings. note: this input has a weak internal pullup. 3los_lvli los level control. the los threshold is set by the input voltage level applied to this pin. figure 6 on page 13 shows the input setting to output threshold mapping. los is disabled when the voltage applied is less than 1 v. 4 slice_lvl i slicing level control. the slicing threshold level is set by applying a volt- age to this pin as described in the slicing level sec- tion of the data sheet. if this pin is tied to gnd, slicing level adjustment is disabled, and the slicing level is set to the midpoint of the differential input signal on din. slicing level becomes active when the voltage applied to the pin is greater than 500 mv. 5 6 refclk+ refclk? isee table2 differential reference clock (optional). when present, the reference clock sets the center operating frequency of the dspll for clock and data recovery. tie refclk+ to vdd and refclk? to gnd to operate without an external reference clock. see table 7 on page 12 for typical reference clock frequencies. gnd pad 1 2 3 4 5 gnd los_lvl refclk+ ratesel slice_lvl 6 7 lol refclk? 21 20 19 18 17 rext reset/cal dout+ vdd vdd 16 15 tdi dout? 8 9 10 11 12 los dsqlch din+ ltr vdd 13 14 vdd din? 28 27 26 25 24 ber_alm ber_lvl clkdsbl nc vdd 23 22 clkout? clkout+
SI5013 rev. 1.4 19 7 lol olvttl loss-of-lock. this output is driven low when the recovered clock frequency deviates from the reference clock by the amount specified in table 4 on page 9. if no exter- nal reference is s upplied, this signal will be active when the internal pll is no longer locked to the incoming data. 8 ltr ilvttl lock-to-reference. when this pin is low, the dspll disregards the data inputs. if an external reference is supplied, the out- put clock locks to the supplied reference. if no external reference is used, the dspll locks the control loop until ltr is released. note: this input has a weak internal pullup. 9 los olvttl loss-of-signal. this output pin is driven low when the input signal is below the threshold set via los_lvl. (los opera- tion is guaranteed only when ac coupling is used on the din inputs.) 10 dsqlch lvttl data squelch. when driven high, this pin forces the data present on dout+ to zero and dout? to one. for normal operation, this pin should be low. dsqlch may be used during los/lol conditions to prevent random data from being presented to the system. note: this input has a weak internal pulldown. 11,14,18,21, 25 vdd 3.3 v supply voltage. nominally 3.3 v. 12 13 din+ din? isee table2 differential data input. clock and data are recovered from the differential signal present on these pins. ac coupling is recom- mended. 15 gnd gnd production test input. this pin is used during production testing and must be tied to gnd for normal operation. 16 17 dout? dout+ ocml differential data output. the data output signal is a retimed version of the data recovered from the signal present on din. it is phase aligned with clkout and is updated on the rising edge of clkout. 19 reset/cal i lvttl reset/calibrate. driving this input high for at least 1 s will reset internal device circuitry. a high to low transition on this pin will force a dspl l calibration. for normal operation, drive this pin low. note: this input has a weak internal pulldown. table 8. SI5013 pin descriptions (continued) pin # pin name i/o signal level description
SI5013 20 rev. 1.4 20 rext external bias resistor. this resistor is used to establish internal bias cur- rents within the device. this pin must be connected to gnd through a 10 k ? ( 1 %) resistor. 22 23 clkout? clkout+ ocml differential clock output. the output clock is recovered from the data signal present on din except when ltr is asserted or the lol state has been entered. 24 clkdsbl i lvttl clock disable. when this input is high, the clkout output drivers are disabled. for normal operation, this pin should be low. note: this input has a weak internal pulldown. 26 ber_lvl i bit error rate level control. the ber threshold level is set by applying a volt- age to this pin. when the ber exceeds the pro- grammed threshold, ber_alm is driven low. if this pin is tied to gnd, ber_alm is disabled. there is no hysteresis. 27 ber_alm olvttl bit error rate alarm. this pin will be driven low to indicate that the ber threshold set by ber_lvl has been exceeded. the alarm will clear after the ber rate has improved by approximately a factor of 2. 28 nc no connect. leave this pin disconnected. gnd pad, 2 gnd gnd supply ground. nominally 0.0 v. the gnd pad found on the bottom of the 28-lead mlp (see figure 16 on page 22) must be connected directly to supply ground. min- imize the ground path inductance for optimal perfor- mance. table 8. SI5013 pin descriptions (continued) pin # pin name i/o signal level description
SI5013 rev. 1.4 21 6. ordering guide part number package voltage lead-free temperature SI5013-x-gm 28-lead mlp 3.3 yes ?40 to 85 c notes: 1. ?x? denotes product revision. 2. add an ?r? at the end of the device to denote tape and reel option; 2500 quantity per reel.
SI5013 22 rev. 1.4 7. package outline figure 16 illustrates the package details for the si501 3. table 9 lists the values fo r the dimensions shown in the illustration. figure 16. 28-lead micro leaded package (mlp) table 9. package diagram dimensions controlling dimension: mm symbol millimeters min nom max a ? 0.85 0.90 a1 0.00 0.01 0.05 b 0.180.230.30 d5.00 bsc d1 4.75 bsc d2 2.95 3.10 3.25 e5.00 bsc e1 4.75 bsc e2 2.95 3.10 3.25 n28 nd 7 ne 7 e0.50 bsc l 0.500.600.75 12 e1/2 e/2 e1 e a n d1 d1/2 d/2 d a1 a b e l (nd?1) xe ref. bottom view top view (ne?1) xe ref. 1 2 3 1 2 3 ba1 e c l section "c?c" scale: none e2 approximate device weight is 62.2 mg. cc d2 n 0.10 cab m 0.05 c 0.10 c a 0.10 c b 2x b c seating plane 2x
SI5013 rev. 1.4 23 d ocument c hange l ist revision 0.2 to revision 1.0 added figure 4, ?pll acquisition time,? on page 6. table 2 on page 7 updated values: supply current updated values: power dissipation updated values: common mode input voltage (refclk) updated values: output common mode voltage table 3 on page 8 updated values: output clock rise time updated values: output clock fall time updated values: clock to data delay t cf-d table 4 on page 9 updated values: jitter tolerance (oc-12) updated values: rms jitter generation updated values: peak-to- peak jitter generation updated values: acquisition time (reference clock applied) updated values: acquisition time (reference-less operation) updated values: freq difference at which receive pll goes out of lock updated values: freq difference at which receive pll goes into lock removed ?hysteresis dependency? figure. added figure 7, ?los signal hysteresis,? on page 13. corrected error: table 8 on page 18?changed description for los_lvl from ?los is disabled when the voltage applied is less than 500 mv? to ?los is disabled when the voltage applied is less than 1.0 v.? revision 1.0 to revision 1.1 corrected ?revision 0.2 to revision 1.0? change list. table 4 on page 9 updated values: jitter tolerance (oc-3) revision 1.1 to revision 1.2 added figure 5, ?los response,? on page 6. updated table 2 on page 7. added ?output common m ode voltage (dout)? with updated values. added ?output common mode voltage (clkout)? with updated values. updated table 3 on page 8. added ?output clock duty cycle?oc-12/3.? added ?loss-of-signal response time? with updated values. updated table 8 on page 18. changed ?clock input? to ?din inputs? for loss of signal updated figure 16, ?28-lead micro leaded package (mlp),? on page 22. updated table 9, ?package diagram dimensions,? on page 22. changed dimension a. changed dimension e2. revision 1.2 to revision 1.3 updated figure 16, ?28-lead micro leaded package (mlp),? on page 22. updated table 9, ?package diagram dimensions,? on page 22. revision 1.3 to revision 1.4 updated "features" on page 1. table 2 on page 7. updated supply current values. updated power dissipation values. updated differential output voltage swing (dout and clkout). table 3 on page 8. added output clock rate values. updated duty cycle values. updated slice accuracy values. table 4 on page 9. updated jitter tolerance values (oc-12 mode). updated acquisition time values. updated reference clocks range. updated refe rence clocks tolerance. "3.typical application schematic" on page 11. added 1% to rext. "4.11.pll performance" on page 14. removed oc-24 note. table 8 on page 18. added no-hysteresis text to ber_lvl. updated "6.ordering guide" on page 21. added ?x? to part number.
SI5013 24 rev. 1.4 c ontact i nformation silicon laboratories inc. 4635 boston lane austin, tx 78735 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: highspeed@silabs.com internet: www.silabs.com silicon laboratories, silicon labs, and dspll are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

▲Up To Search▲

Price & Availability of SI5013

	To Download SI5013 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .